Friday, 18 September 2020 15:15

Cypress’ 32-bit Arm® Cortex®-M4 Cortex-M0+ PSoC® 6

PSoC® 6 bridges the gap between expensive, power hungry application processors and low performance microcontrollers (MCUs). The ultra low power PSoC 6 MCU architecture offers the processing performance needed by IoT devices, eliminating the tradeoffs between power and performance. The PSoC 6 MCU contains a dual CPU architecture, with both CPUs on a single chip. It has an Arm® Cortex® M4 for high performance tasks, and an Arm Cortex M0+ for low-power tasks. With security built-in, your IoT system is protected.
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  • Single or Dual Arm® Cortex®-M4F and Arm® Cortex®-M0+ CPUs

Whether you only need an ultra low-power programmable solution or high-performance, secure, dual-CPU programmability, the PSoC 6 family can support your needs. The 150-MHz Arm® Cortex®-M4F CPU has single-cycle multiply with floating point and a memory protection unit (MPU) while the 100-MHz Arm® Cortex®-M0+ CPU has single-cycle multiply and an MPU. The CPUs are designed for battery and other low-power applications allowing you to select a 1.1V or 0.9V operation voltage. The flash memory has two caches, one for each CPU.  There are up to three DMA controllers with up to 16 channels each.

  • Bluetooth Low Energy (Bluetooth Smart)

Members of the PSoC 63 and PSoC 64 lines with Bluetooth Low Energy radios on chip comply to the Bluetooth 5.0 specification. They have a 2.4 GHz RF transceiver with a 50 Ω antenna drive. The Link Layer supports four simultaneous connections with 2 Mbps LE data rate.

  • Low-Power 1.7-V to 3.6-V Operation

Beyond merely a low-power core, the PSoC 6 programmable processor line has six power modes for fine-grained power management. This was built for extended battery life without sacrificing performance. PSoC 6 is built on an ultra-low power 40 nm process and uses as little as 22 uA/MHz in active power mode and 7 uA in deep sleep mode with 64 KB SRAM retention. 

  • Programmable Analog

Flexibility, low-power, and ease-of-use are the PSoC heritage. The PSoC 6 is no exception. It includes PSoC's best-in-class programmable analog with a 12-bit 1-Msps SAR ADC with differential and single-ended modes and a 16-channel sequencer with result averaging. The PSoC 6 also includes two low-power comparators which are even available in Deep Sleep and Hibernate modes, and two opamps with low-power operation modes.

  • CapSense®

Cypress’ industry-leading CapSense brings elegant, reliable, and simple capacitive touch sensing functions to applications requiring touch buttons, sliders, wheels, trackpads, and touchscreens.  CapSense can also be used for advanced features such as proximity sensing, hover and glove touch, and liquid level sensing.  CapSense supports both self-capacitance (CSD) as well a mutual-capacitance (CSX) sensing methods with best-in-class signal-to-noise ratio (SNR) for robust sensing under harsh and noisy conditions including liquid tolerance.  Cypress’ SmartSense™ auto-tuning technology help you avoid complex manual tuning processes allowing you to get your product to market quickly.

  • Security

The PSoC 6 family of MCUs come equipped with secure features such as hardware cryptographic accelerators, a true-random number generator (TRNG), and the protection units used to implement up to 8 protection contexts.  The PSoC 64 line comes with validated security firmware to help you accelerate your secure design implementation.  The PSoC 64 secure boot product comes with a pre-established root-of-trust that can enabling a developer to easily implement secure boot and secure firmware updates.  In addition to the features in the secure boot product, the PSoC 64 standard secure product comes with Trusted Firmware-M (TF-M) firmware enabling you to establish isolated execution environments.

 
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